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for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ________________general description the max1630a?ax1635a are buck-topology, step- down, switch-mode, power-supply controllers that gener- ate logic-supply voltages in battery-powered systems. these high-performance, dual-/triple-output devices include on-board power-up sequencing, power-good signaling with delay, digital soft-start, secondary winding control, low-dropout circuitry, internal frequency-com- pensation networks, and automatic bootstrapping. up to 96% efficiency is achieved through synchronous rectification and maxim? proprietary idle mode control scheme. efficiency is greater than 80% over a 1000:1 load-current range, which extends battery life in system- suspend or standby mode. excellent dynamic response corrects output load transients caused by the latest dynamic-clock cpus within five 300khz clock cycles. strong 1a on-board gate drivers ensure fast external n-channel mosfet switching. these devices feature a logic-controlled and synchroniz- able, fixed-frequency, pulse-width-modulation (pwm) operating mode. this reduces noise and rf interference in sensitive mobile communications and pen-entry appli- cations. asserting the skip pin enables fixed-frequency mode for lowest noise under all load conditions. the max1630a?ax1635a include two pwm regulators, adjustable from 2.5v to 5.5v with fixed 5.0v and 3.3v modes. all these devices include secondary feedback regulation, and the max1630a/max1632a/max1633a/ max1635a each contain 12v/120ma linear regulators. the max1631a/max1634a include a secondary feed- back input (secfb), plus a control pin (steer) that selects which pwm (3.3v or 5v) receives the secondary feedback signal. secfb provides a method for adjusting the secondary winding voltage regulation point with an external resistor-divider, and is intended to aid in creating auxiliary voltages other than fixed 12v. the max1630a/max1631a/max1632a contain internal output overvoltage and undervoltage protection features. the max1630a family has improved rf immunity over the max1630 family. ________________________applications notebook and subnotebook computers pdas and mobile communicators desktop cpu local dc-dc converters ____________________________features ? 96% efficiency ? +4.2v to +30v input range ? 2.5v to 5.5v dual adjustable outputs ? selectable 3.3v and 5v fixed or adjustable outputs (dual mode) ? 12v linear regulator ? adjustable secondary feedback (max1631a/max1634a) ? 5v/50ma linear regulator output ? precision 2.5v reference output ? programmable power-up sequencing ? power-good (reset) output ? output overvoltage protection (max1630a/max1631a/max1632a) ? output undervoltage shutdown (max1630a/max1631a/max1632a) ? 200khz/300khz low-noise, fixed-frequency operation ? low-dropout, 99% duty-factor operation ? 2.5mw typical quiescent power (+12v input, both smpss on) ? 4a typical shutdown current ? 28-pin ssop package max1630a?ax1635a multi-output, low-noise power-supply controllers for notebook computers ________________________________________________________________ maxim integrated products 1 5v linear 12v linear power-up sequence power- good 3.3v smps 5v smps reset on/off +5v (rtc) +3.3v input +5v +12v ________________functional diagram 19-3518; rev 1; 8/05 part max1630a eai -40? to +85? temp range pin-package 28 ssop evaluation kit available _______________ordering information + denotes lead-free package. ordering information continued at end of data sheet. pin configurations and selector guide appear at end of data sheet. idle mode and dual mode are trademarks of maxim integrated products, inc.
max1630a?ax1635a multi-output, low-noise power-supply controllers for notebook computers 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v+ = 15v, both pwms on, sync = vl, vl load = 0ma, ref load = 0ma, skip = 0v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v+ to gnd ..............................................................-0.3v to +36v pgnd to gnd.....................................................................?.3v vl to gnd ................................................................-0.3v to +6v bst3, bst5 to gnd ...............................................-0.3v to +36v lx3 to bst3..............................................................-6v to +0.3v lx5 to bst5..............................................................-6v to +0.3v ref, sync, seq, steer, skip , time/on5, secfb, reset to gnd .......................................-0.3v to +6v v dd to gnd ............................................................-0.3v to +20v run/on3, shdn to gnd.............................-0.3v to (v+ + 0.3v) 12out to gnd ...........................................-0.3v to (v dd + 0.3v) dl3, dl5 to pgnd........................................-0.3v to (vl + 0.3v) dh3 to lx3 ...............................................-0.3v to (bst3 + 0.3v) dh5 to lx5 ...............................................-0.3v to (bst5 + 0.3v) vl, ref short to gnd ................................................momentary 12out short to gnd..................................................continuous ref current...........................................................+5ma to -1ma vl current.........................................................................+50ma 12out current ...............................................................+200ma v dd shunt current ............................................................+15ma operating temperature ranges max163_acai ....................................................0? to +70? max163_aeai .................................................-40? to +85? storage temperature range .............................-65? to +160? continuous power dissipation (t a = +70?) ssop (derate 9.52mw/? above +70?) ....................762mw lead temperature (soldering, 10s) .................................+300? conditions v 4.2 30.0 input voltage range units min typ max parameter either smps v+ = 4.2v to 30v, csh3?sl3 = 0v, csl3 tied to fb3 v ref 5.5 v 2.42 2.5 2.58 3v output voltage in adjustable mode output voltage adjust range either smps, 5.2v < v+ < 30v %/v 0.03 either smps, 0v < csh_- csl_ < 80mv line regulation dual mode comparator % -2 v 0.5 1.1 adjustable-mode threshold voltage load regulation sync = vl from enable to 95% full current limit with respect to f osc (note 1) 270 300 330 clks 512 skip = 0v, not tested soft-start ramp time mv 10 25 40 idle mode threshold sync = 0v khz 170 200 230 oscillator frequency v+ = 4.2v to 30v, 0mv < csh3?sl3 < 80mv, fb3 = 0v v 3.20 3.39 3.47 3v output voltage in fixed mode v+ = 4.2v to 30v, csh5?sl5 = 0v, csl5 tied to fb5 v 2.42 2.5 2.58 5v output voltage in adjustable mode v+ = 5.2v to 30v, 0mv < csh?sl5 < 80mv, fb5 = 0v v 4.85 5.13 5.25 5v output voltage in fixed mode sync = vl 97 98 sync = 0v (note 2) % 98 99 maximum duty factor csh3?sl3 or csh5?sl5 80 100 120 skip = vl or v dd < 13v or secfb < 2.44v mv -50 -100 -150 current-limit threshold main smps controllers
max1630a?ax1635a multi-output, low-noise power-supply controllers for notebook computers _______________________________________________________________________________________ 3 electrical characteristics (continued) (v+ = 15v, both pwms on, sync = vl, vl load = 0ma, ref load = 0ma, skip = 0v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) v+ = vl = 0v, csl3 = csh3 = csl5 = csh5 = 5.5v ? 0.01 10 not tested current-sense input leakage current not tested rising edge, hysteresis = 1% (note 3) v dd < 13v or secfb < 2.44v v 18 20 ? 1 falling edge (max1631a/max1634a) dl pulse width falling edge (note 3) v dd shunt threshold v 2.44 2.60 v 13 14 conditions v dd regulation threshold secfb regulation threshold v dd = 20v (note 3) v dd = 5v, off mode (notes 3, 4) ? 30 v dd leakage current ma 10 v dd shunt sink current ns 200 ns 200 sync input high pulse width sync input low pulse width 13v < v dd < 18v, 0ma < i load < 120ma v 11.65 12.1 12.50 12out output voltage units min typ max parameter not tested ns 200 sync rise/fall time khz 240 350 sync input frequency range v dd = 18v, run mode, no 12out load 12out forced to 11v, v dd = 13v ? 50 100 ma 150 12out current limit quiescent v dd current rising edge of csl5, hysteresis = 1% falling edge, hysteresis = 1% v 4.2 4.5 4.7 v 3.5 3.6 3.7 vl undervoltage lockout fault threshold vl switchover threshold shdn = v+, run/on3 = time/on5 = 0v, 5.3v < v+ < 30v, 0ma < i load < 50ma v 4.7 5.1 vl output voltage falling edge v 1.8 2.4 ? 10 ref sink current ref fault lockout voltage v+ = 4v to 24v, shdn = 0v v+ = 4.2v to 5.5v, both smpss off, includes current into shdn ? 410 ? 50 200 v+ standby supply current in dropout v+ shutdown supply current v+ = 5.5v to 30v, both smpss off, includes current into shdn vl switched over to csl5, 5v smps on ? 30 60 ? 550 v+ operating supply current v+ standby supply current 0? < i load < 50? no external load (note 5) 12.5 v 2.45 2.5 2.55 ref output voltage 2.5 4 both smpss enabled, fb3 = fb5 = 0v, csl3 = csh3 = 3.5v, csl5 = csh5 = 5.3v mw 1.5 4 quiescent power consumption (note 3) max1631a/ max1634a 0ma < i load < 5ma mv 100.0 ref load regulation flyback controller 12v linear regulator (note 3) internal regulator and reference
max1630a?ax1635a multi-output, low-noise power-supply controllers for notebook computers 4 _______________________________________________________________________________________ note 1: each of the four digital soft-start levels is tested for functionality; the steps are typically in 20mv increments. note 2: high duty-factor operation supports low input-to-output differential voltages, and is achieved at a lowered operating frequency (see overload and dropout operation section). note 3: max1630a/max1632a/max1633a/max1635a only. note 4: off mode for the 12v linear regulator occurs when the smps that has flyback feedback (v dd ) steered to it is disabled. in situations where the main outputs are being held up by external keep-alive supplies, turning off the 12out regulator pre- vents a leakage path from the output-referred flyback winding, through the rectifier, and into v dd . note 5: since the reference uses vl as its supply, the reference? v+ line-regulation error is insignificant. electrical characteristics (continued) (v+ = 15v, both pwms on, sync = vl, vl load = 0ma, ref load = 0ma, skip = 0v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) typical hysteresis = +10? from each smps enabled, with respect to f osc ? 150 clks 5000 6144 7000 with respect to unloaded output voltage output undervoltage lockout time thermal shutdown threshold with respect to f osc falling edge, csl_ driven 2% below reset trip threshold clks 27,000 32,000 37,000 ? 1.5 with respect to unloaded output voltage, falling edge; typical hysteresis = 1% reset propagation delay reset delay time % -7 -5.5 -4 conditions reset trip threshold reset , i sink = 4ma run/on3, skip , time/on5 (seq = ref), shdn , steer, sync, seq; v pin = 0v or 3.3v v 0.4 ? ? input leakage current logic output low voltage csl_ driven 2% above overvoltage trip threshold ? fb3, fb5; secfb = 2.6v 1.5 overvoltage-fault propagation delay na 150 with respect to unloaded output voltage % 60 70 80 feedback input leakage current output undervoltage threshold % 4710 overvoltage trip threshold run/on3, skip , time/on5 (seq = ref), shdn , steer, sync run/on3, skip , time/on5 (seq = ref), shdn , steer, sync v 2.4 v 0.6 logic input low voltage logic input high voltage units min typ max parameter high or low dl3, dh3, dl5, dh5; forced to 2v 1.5 7 a 1 gate driver sink/source current gate driver on-resistance reset = 3.5v ma 1 logic output high current time/on5 = 0v, seq = 0v or vl seq = 0v or vl ? 2.5 3 3.5 v 2.4 2.6 time/on5 input trip level time/on5 source current time/on5; run/on3 = 0v, seq = 0v or vl 15 80 time/on5 on-resistance fault detection (max1630a/max1631a/max1632a) inputs and outputs reset
max1630a?ax1635a multi-output, low-noise power-supply controllers for notebook computers _______________________________________________________________________________________ 5 100 50 0.001 0.01 0.1 1 10 efficiency vs. 5v output current 60 max1630a/35a toc01 5v output current (a) efficiency (%) 70 80 90 on5 = 5v on3 = 0v f = 300khz max1631a/max1634a v+ = 6v v+ = 15v 100 50 0.001 0.01 0.1 1 10 efficiency vs. 3.3v output current 60 max1630a/35a toc02 3.3v output current (a) efficiency (%) 70 80 90 on3 = on5 = 5v f = 300khz max1631a/max1634a v+ = 6v v+ = 15v 800 0 15 20 max1632a/max1635a maximum 15v v dd output current vs. supply voltage 600 max1630a/35a toc03 supply voltage (v) maximum output current (ma) 0 200 10 400 5 v dd > 13v 5v regulating 5v load = 0a 5v load = 3a 500 0 15 20 max1630a/max1633a maximum 15v v dd output current vs. supply voltage 400 max1630a/35a toc04 supply voltage (v) maximum output current (ma) 0 200 100 10 300 5 v dd > 13v 3.3v regulating 3.3v load = 0a 3.3v load = 3a 10,000 1 030 standby input current vs. input voltage 1000 max1630a/35a toc07 input voltage (v) input current ( a) 15 10 510 25 100 20 on3 = on5 = 0v no load 30 0 5 030 pwm mode input current vs. input voltage max1630a/35a toc05 input voltage (v) input current (ma) 15 10 15 510 25 20 25 20 on3 = on5 = 5v skip = vl no load 10 0.01 030 idle mode input current vs. input voltage max1630a/35a toc06 input voltage (v) input current (ma) 15 0.1 510 25 1 20 on3 = on5 = 5v skip = 0v no load 10 0 030 shutdown input current vs. input voltage 8 max1630a/35a toc08 input voltage (v) input current ( a) 15 4 2 510 25 6 20 shdn = 0v 1000 1 0.001 0.1 10 1 minimum v in to v out differential vs. 5v output current 10 100 max1630a/35a toc09 5v output current (a) min v in to v out differential (mv) 0.01 5v, 3a circuit v out > 4.8v f = 300khz __________________________________________typical operating characteristics (circuit of figure 1, 3a table 1 components, t a = +25?, unless otherwise noted.)
__________________________________________________________________________ pin description max1630a?ax1635a multi-output, low-noise power-supply controllers for notebook computers 6 _______________________________________________________________________________________ ____________________________________t ypical operating characteristics (continued) (circuit of figure 1, 3a table 1 components, t a = +25?, unless otherwise noted.) 1000 0.1 0.1 10 1000 100 switching frequency vs. load current 10 1 100 max1630a/35a toc010 load current (ma) switching frequency (khz) 1 +5v, v in = 15v +3.3v, v in = 15v +3.3v, v in = 6v +5v, v in = 6v 5.00 4.90 50 60 vl regulator output voltage vs. output current 4.98 max1630a/35a toc11 output current (ma) vl output voltage (v) 0 4.94 4.92 30 40 4.96 10 20 v in = 15v on3 = on5 = 0v 2.510 2.480 2.485 56 ref output voltage vs. output current 2.505 max1630a/35a toc12 output current (ma) ref output voltage (v) 0 2.495 2.490 34 2.500 12 v in = 15v on3 = on5 = 0v 2ms/div startup waveforms run 5v/div 3.3v output 2v/div time 5v/div 5v output 5v/div seq = vl, 0.015 f capacitor on-time max1630a/35a toc13 4 1 csh3 current-sense input for the 3.3v smps. current-limit level is 100mv referred to csl3. steer (max1631a/ max1634a) logic-control input for secondary feedback. selects the pwm that uses a transformer and secondary feedback signal (secfb): steer = gnd: 3.3v smps uses transformer steer = vl: 5v smps uses transformer pin name function 2 csl3 current-sense input. also serves as the feedback input in fixed-output mode. 12out (max1630a/ 32a/33a/35a) 12v/120ma linear regulator output. input supply comes from v dd . bypass 12out to gnd with 1? minimum. 3 fb3 feedback input for the 3.3v smps; regulates at fb3 = ref (approx. 2.5v) in adjustable mode. fb3 is a dual mode input that also selects the 3.3v fixed output voltage setting when tied to gnd. connect fb3 to a resistor-divider for adjustable-output mode.
max1630a?ax1635a multi-output, low-noise power-supply controllers for notebook computers _______________________________________________________________________________________ 7 _________________________________________________pin description (continued) 5 26 lx3 switching node (inductor) connection. can swing 2v below ground without hazard. 27 dh3 gate-drive output for the 3.3v, high-side n-channel switch. dh3 is a floating driver output that swings from lx3 to bst3, riding on the lx3 switching node voltage. 28 run/on3 on/ off control input. see power-up sequencing and on/ off controls section . 24 dl3 gate-drive output for the low-side synchronous-rectifier mosfet. swings 0v to vl. 25 bst3 boost capacitor connection for high-side gate drive (0.1?) secfb (max1631a/ max1634a) secondary winding feedback input. normally connected to a resistor-divider from an auxiliary output. secfb regulates at v secfb = 2.5v (see secondary feedback regulation loop section). tie to vl if not used. v dd (max1630a/ 32a/33a/35a) supply voltage input for the 12out linear regulator. also connects to an internal resistor-divider for secondary winding feedback, and to an 18v overvoltage shunt regulator clamp. 21 vl 5v internal linear-regulator output. vl is also the supply voltage rail for the chip. after the 5v smps output has reached +4.5v (typical), vl automatically switches to the output voltage through csl5 for bootstrapping. bypass to gnd with 4.7?. vl supplies up to 25ma for external loads. 22 v+ battery voltage input, +4.2v to +30v. bypass v+ to pgnd close to the ic with a 0.22? capacitor. connects to a linear regulator that powers vl. 23 shdn shutdown control input, active low. logic threshold is set at approximately 1v. for automatic startup, connect shdn to v+ through a 220k resistor and bypass shdn to gnd with a 0.01? capacitor. 13 csl5 current-sense input for the 5v smps. also serves as the feedback input in fixed-output mode, and as the bootstrap supply input when the voltage on csl5/vl is > 4.5v. 14 csh5 current-sense input for the 5v smps. current-limit level is 100mv referred to csl5. 17 lx5 switching node (inductor) connection. can swing 2v below ground without hazard. 18 bst5 boost capacitor connection for high-side gate drive (0.1?) 19 dl5 gate-drive output for the low-side synchronous-rectifier mosfet. swings 0v to vl. 20 pgnd power ground 15 seq pin-strap input that selects the smps power-up sequence: seq = gnd: 5v before 3.3v, reset output determined by both outputs seq = ref: separate on3/on5 controls, reset output determined by 3.3v output seq = vl: 3.3v before 5v, reset output determined by both outputs 16 dh5 gate-drive output for the 5v, high-side n-channel switch. dh5 is a floating driver output that swings from lx5 to bst5, riding on the lx5 switching node voltage. 12 fb5 feedback input for the 5v smps; regulates at fb5 = ref (approximately 2.5v) in adjustable mode. fb5 is a dual mode input that also selects the 5v fixed output voltage setting when tied to gnd. connect fb5 to a resistor-divider for adjustable-output mode. 8 gnd low-noise analog ground and feedback reference point 9 ref 2.5v reference voltage output. bypass to gnd with 1? minimum. 10 skip logic-control input that disables idle mode when high. connect to gnd for normal use. 11 reset active-low timed reset output. reset swings gnd to vl. goes high after a fixed 32,000 clock-cycle delay following power-up. 6 sync oscillator synchronization and frequency select. tie to vl for 300khz operation; tie to gnd for 200khz operation. can be driven at 240khz to 350khz for external synchronization. 7 time/on5 dual-purpose timing capacitor pin and on/ off control input. see power-up sequencing and on/ off controls section. name function pin
_______standard application circuit the basic max1631a/max1634a dual-output 3.3v/5v buck converter (figure 1) is easily adapted to meet a wide range of applications with inputs up to 28v by substituting components from table 1. these circuits represent a good set of tradeoffs between cost, size, and efficiency, while staying within the worst-case specification limits for stress-related parameters, such as capacitor ripple current. do not change the frequen- cy of these circuits without first recalculating compo- nent values (particularly inductance value at maximum battery voltage). adding a schottky rectifier across each synchronous rectifier improves the efficiency of these circuits by approximately 1%, but this rectifier is otherwise not needed because the mosfets required for these circuits typically incorporate a high-speed sili- con diode from drain to source. use a schottky rectifier rated at a dc current equal to at least 1/3 of the load current. max1630a?ax1635a multi-output, low-noise power-supply controllers for notebook computers 8 _______________________________________________________________________________________ max1631a max1634a v+ shdn vl secfb input on/off c3 gnd ref seq 1 f +2.5v always on *1a schottky diode required for the max1631a (see output overvoltage protection section). +5v always on q1 5v on/off 3.3v on/off q4 0.1 f 0.1 f l2 r2 +3.3v output c2 * 4.7 f 0.1 f 4.7 f 0.1 f 10 0.1 f q3 0.1 f dl3 csh3 csl3 fb3 reset reset output skip steer q2 l1 r1 +5v output c1 dl5 lx5 dh5 bst5 bst3 sync dh3 lx3 pgnd csl5 csh5 run/on3 time/on5 fb5 * figure 1. standard 3.3v/5v application circuit (max1631a/max1634a)
max1630aa?ax1635a multi-output, low-noise power-supply controllers for notebook computers _______________________________________________________________________________________ 9 input range application table 1. component selection for standard 3.3v/5v application table 2. component suppliers 4.75v to 18v pda 2a 4.75v to 28v notebook 3a 4.75v to 24v workstation 4a frequency 300khz 1/2 ir irf7301; 1/2 siliconix si9925dq; or 1/2 motorola mmdf3n03hd or mmdf4n01hd (10v max) 300khz ir irf7403 or irf7401 (18v max); siliconix si4412dy; or motorola mmsf5n03hd or mmsf5n02hd (18v max) 200khz ir irf7413 or siliconix si4410dy q1, q3 high-side mosfets q2, q4 low-side mosfets 1/2 ir irf7301; 1/2 siliconix si9925dq; or 1/2 motorola mmdf3n03hd or mmdf4n01hd (10v max) 10?, 30v sanyo os-con; 22?, 35v avx tps; or sprague 594d ir irf7403 or irf7401 (18v max); siliconix si4412dy; or motorola mmsf5n03hd or mmsf5n02hd (18v max) 2 x 10?, 30v sanyo os-con; 2 x 22?, 35v avx tps; or sprague 594d ir irf7413 or siliconix si4410dy 3 x 10?, 30v sanyo os-con; 4 x 22?, 35v avx tps; or sprague 595d c1, c2 output capacitors 220?, 10v avx tps or sprague 595d 0.033 irc lr2010-01-r033 or dale wsl2010-r033-f 2 x 220?, 10v avx tps or sprague 595d 0.02 irc lr2010-01-r020 or dale wsl2010-r020-f 4 x 220?, 10v avx tps or sprague 595d 0.012 dale wsl2512-r012-f r1, r2 resistors c3 input capacitor 15?, 2.4a ferrite coilcraft do3316p-153 or sumida cdrh125-150 10?, 4a ferrite coilcraft do3316p-103 or sumida cdrh125-100 4.7?, 5.5a ferrite coilcraft do3316-472 or 5.2?, 6.5a ferrite sumida cdrh127-5r2mc l1, l2 inductors avx (1) 803-626-3123 (1) 516-435-1824 factory fax (country code) 803-946-0690 516-435-1110 usa phone coilcraft (1) 847-639-1469 847-639-6400 central semiconductor company coiltronics (1) 561-241-9339 (1) 605-665-1627 561-241-7876 605-668-4131 international rectifier (ir) (1) 310-322-3332 310-322-3331 dale irc (1) 512-992-3377 (1) 714-960-6492 512-992-7900 714-969-2491 matsuo motorola (1) 602-994-6430 (81) 3-3494-7414 factory fax (country code) 602-303-5454 805-867-2555* usa phone siliconix (1) 408-970-3950 (1) 603-224-1430 sanyo (81) 7-2070-1174 408-988-8000 619-661-6835 603-224-1961 sumida (81) 3-3607-5144 847-956-0666 sprague tdk (1) 847-390-4428 (1) 702-831-3521 847-390-4373 702-831-0140 transpower technologies niec company murata-erie (1) 814-238-0490 814-237-1431 * distributor load current component
max1630aa?ax1635a multi-output, low-noise power-supply controllers for notebook computers 10 ______________________________________________________________________________________ _______________detailed description the max1630a is a dual, bicmos, switch-mode power- supply controller designed primarily for buck-topology regulators in battery-powered applications where high effi- ciency and low quiescent supply current are critical. light- load efficiency is enhanced by automatic idle mode operation, a variable-frequency pulse-skipping mode that reduces transition and gate-charge losses. each step- down, power-switching circuit consists of two n-channel mosfets, a rectifier, and an lc output filter. the output voltage is the average ac voltage at the switching node, which is regulated by changing the duty cycle of the mosfet switches. the gate-drive signal to the n-channel high-side mosfet must exceed the battery voltage, and is provided by a flying-capacitor boost circuit that uses a 100nf capacitor connected to bst_. devices in the max1630a family contain 10 major circuit blocks (figure 2). the two pwm controllers each consist of a dual mode feedback network and multiplexer, a multi-input pwm comparator, high-side and low-side gate drivers, and logic. the max1630a/max1631a/max1632a contain fault-protection circuits that monitor the main pwm out- puts for undervoltage and overvoltage. a power-on sequence block controls the power-up timing of the main pwms and determines whether one or both of the outputs are monitored for undervoltage faults. the max1630a/max1632a/max1633a/max1635a include a secondary feedback network and 12v linear regulator to generate a 12v output from a coupled-inductor fly- back winding. the max1631a/max1634a have an secfb instead, which allows a quasi-regulated, adjustable-output, coupled-inductor flyback winding to be attached to either the 3.3v or the 5v main inductor. bias generator blocks include the 5v ic internal rail (vl) linear regulator, 2.5v precision reference, and automatic bootstrap switchover circuit. the pwms share a com- mon 200khz/300khz synchronizable oscillator. these internal ic blocks are not powered directly from the battery. instead, the 5v vl linear regulator steps down the battery voltage to supply both vl and the gate drivers. the synchronous-switch gate drivers are directly powered from vl, while the high-side switch gate drivers are indirectly powered from vl through an external diode-capacitor boost circuit. an automatic bootstrap circuit turns off the +5v linear regulator and powers the ic from the 5v pwm output voltage if the output is above 4.5v. pwm controller block the two pwm controllers are nearly identical. the only differences are fixed output settings (3.3v vs. 5v), the vl/csl5 bootstrap switch connected to the +5v pwm, and secfb. the heart of each current-mode pwm con- troller is a multi-input, open-loop comparator that sums three signals: the output voltage error signal with respect to the reference voltage, the current-sense sig- nal, and the slope compensation ramp (figure 3). the pwm controller is a direct-summing type, lacking a tra- ditional error amplifier and the phase shift associated with it. this direct-summing configuration approaches ideal cycle-by-cycle control over the output voltage. when skip = low, idle mode circuitry automatically optimizes efficiency throughout the load current range. idle mode dramatically improves light-load efficiency by reducing the effective frequency, which reduces switching losses. it keeps the peak inductor current above 25% of the full current limit in an active cycle, allowing subsequent cycles to be skipped. idle mode transitions seamlessly to fixed-frequency pwm opera- tion as load current increases. with skip = high, the controller always operates in fixed-frequency pwm mode for lowest noise. each pulse from the oscillator sets the main pwm latch that turns on the high-side switch for a period determined by the duty factor (approximately v out /v in ). as the high-side switch turns off, the synchronous rectifier latch sets; 60ns later, the low-side switch turns on. the low-side switch stays on until the beginning of the next clock cycle. in pwm mode, the controller operates as a fixed- frequency current-mode controller where the duty ratio is set by the input/output voltage ratio. the current- mode feedback system regulates the peak inductor table 3. skip pwm table low light load current pulse-skipping, supply cur- rent = 250? at v in = 12v, discontinuous inductor current description low heavy constant-frequency pwm, continuous inductor current skip idle mode pwm high light pwm constant-frequency pwm, continuous inductor current pwm high heavy constant-frequency pwm, continuous inductor current
max1630a?ax1635a multi-output, low-noise power-supply controllers for notebook computers ______________________________________________________________________________________ 11 lpf 60khz ref 1.75v 2.68v 2.388v r3 r4 - + + - 4.5v ref 2.5v ref 200khz to 300khz osc 5v pwm logic 5v linear reg vl bst3 dh3 lx3 dl3 +3.3v vl on/off input +5v always on csl5 shdn v+ sync 12v linear reg +12v 13v bst5 raw +15v dh5 dl5 vl pgnd csh5 csl5 csh3 csl3 fb5 reset seq 2.6v 1v 0.6v 0.6v vl gnd run/on3 time/on5 ref lx5 +5v 12out v dd in secfb 3.3v pwm logic ref outputs up - + - + + - - + - + + - + - lpf 60khz timer power-on sequence logic r1 r2 fb3 - + + - max1632a ov/uv fault figure 2. max1632a block diagram
max1630a?ax1635a multi-output, low-noise power-supply controllers for notebook computers 12 ______________________________________________________________________________________ shoot- through control r q 30mv r q level shift 1 s single-shot 1x main pwm comparator osc level shift current limit synchronous rectifier control ref shdn ck -100mv csh_ csl_ from feedback divider bst_ dh_ lx_ vl dl_ pgnd s s slope comp skip ref secfb counter dac soft-start figure 3. pwm controller detailed block diagram
max1630a?ax1635a multi-output, low-noise power-supply controllers for notebook computers ______________________________________________________________________________________ 13 figure 4. main pwm comparator block diagram fb_ ref csh_ csl_ slope compensation vl i1 r1 r2 to pwm logic output driver uncompensated high-speed level translator and buffer i2 i3 v bias current value as a function of the output-voltage error signal. in continuous-conduction mode, the average inductor current is nearly the same as the peak current, so the circuit acts as a switch-mode transconductance amplifier. this pushes the second output lc filter pole, normally found in a duty-factor-controlled (voltage- mode) pwm, to a higher frequency. to preserve inner- loop stability and eliminate regenerative inductor current ?taircasing,?a slope compensation ramp is summed into the main pwm comparator to make the apparent duty factor less than 50%. the max1630a family uses a relatively low loop gain, allowing the use of lower cost output capacitors. the rel- ative gains of the voltage-sense and current-sense inputs are weighted by the values of current sources that bias three differential input stages in the main pwm comparator (figure 4). the relative gain of the voltage comparator to the current comparator is internally fixed at k = 2:1. the low loop gain results in the 2% typical load-regulation error. the low value of loop gain helps reduce output filter capacitor size and cost by shifting the unity-gain crossover frequency to a lower level. the output filter capacitors (figure 1, c1 and c2) set a dominant pole in the feedback loop that must roll off the loop gain to unity before encountering the zero intro- duced by the output capacitor? parasitic resistance (esr) (see the design procedure section). a 60khz pole-zero cancellation filter provides additional rolloff above the unity-gain crossover. this internal 60khz low- pass compensation filter cancels the zero due to filter capacitor esr. the 60khz filter is included in the loop in both fixed-output and adjustable-output modes. synchronous rectifier driver (dl) synchronous rectification reduces conduction losses in the rectifier by shunting the normal schottky catch diode with a low-resistance mosfet switch. also, the synchro- nous rectifier ensures proper startup of the boost gate- driver circuit. if the synchronous power mosfets are omitted for cost or other reasons, replace them with a small-signal mosfet, such as a 2n7002. if the circuit is operating in continuous-conduction mode, the dl drive waveform is the complement of the dh high- side drive waveform (with controlled dead time to prevent cross-conduction or ?hoot-through?. in discontinuous (light-load) mode, the synchronous switch is turned off as the inductor current falls through zero. the synchronous rectifier works under all operating conditions, including idle mode. the secfb signal further controls the syn- chronous switch timing to improve mul tiple-output cross- regulation (see the secondary feedback regulation loop section).
max1630a?ax1635a multi-output, low-noise power-supply controllers for notebook computers 14 ______________________________________________________________________________________ internal vl and ref supplies an internal regulator produces the +5v supply (vl) that powers the pwm controller, logic, reference, and other blocks within the ic. this 5v low-dropout linear regula- tor supplies up to 25ma for external loads, with a reserve of 25ma for supplying gate-drive power. bypass vl to gnd with 4.7?. important: ensure that vl does not exceed 6v. measure vl with the main output fully loaded. if it is pumped above 5.5v, either excessive boost diode capacitance or excessive ripple at v+ is the probable cause. use only small-signal diodes for the boost cir- cuit (10ma to 100ma schottky or 1n4148 are pre- ferred), and bypass v+ to pgnd with 4.7? directly at the package pins. the 2.5v reference (ref) is accurate to ?% over tem- perature, making ref useful as a precision system ref- erence. bypass ref to gnd with 1? minimum. ref can supply up to 5ma for external loads. (bypass ref with a minimum 1f/ma reference load current.) however, if extremely accurate specifications for both the main output voltages and ref are essential, avoid loading ref more than 100?. loading ref reduces the main output voltage slightly, because of the refer- ence load-regulation error. when the 5v main output voltage is above 4.5v, an internal p-channel mosfet switch connects csl5 to vl, while simultaneously shutting down the vl linear regulator. this action bootstraps the ic, powering the internal circuitry from the output voltage, rather than through a linear regulator from the battery. boot- strapping reduces power dissipation due to gate charge and quiescent losses by providing that power from a 90%-efficient switch-mode source, rather than from a much less efficient linear regulator. boost high-side gate-drive supply (bst3 and bst5) gate-drive voltage for the high-side n-channel switches is generated by a flying-capacitor boost circuit (figure 2). the capacitor between bst_ and lx_ is alternately charged from the vl supply and placed par- allel to the high-side mosfet? gate-source terminals. on startup, the synchronous rectifier (low-side mosfet) forces lx_ to 0v and charges the boost capacitors to 5v. on the second half-cycle, the smps turns on the high-side mosfet by closing an internal switch between bst_ and dh_. this provides the nec- essary enhancement voltage to turn on the high-side switch, an action that ?oosts?the 5v gate-drive signal above the battery voltage. ringing at the high-side mosfet gate (dh3 and dh5) in discontinuous-conduction mode (light loads) is a nat- ural operating condition. it is caused by residual ener- gy in the tank circuit, formed by the inductor and stray capacitance at the switching node, lx. the gate-drive negative rail is referred to lx, so any ringing there is directly coupled to the gate-drive output. current-limiting and current-sense inputs (csh and csl) the current-limit circuit resets the main pwm latch and turns off the high-side mosfet switch whenever the voltage difference between csh and csl exceeds 100mv. this limiting is effective for both current flow directions, putting the threshold limit at ?00mv. the tolerance on the positive current limit is ?0%, so the external low-value sense resistor (r1) must be sized for 80mv/i peak , where i peak is the required peak inductor current to support the full load current, while compo- nents must be designed to withstand continuous cur- rent stresses of 120mv/r1. for breadboarding or for very-high-current applications, it may be useful to wire the current-sense inputs with a twisted pair, rather than pc traces. (this twisted pair need not be anything special; two pieces of wire-wrap wire twisted together are sufficient.) this reduces the possible noise picked up at csh_ and csl_, which can cause unstable switching and reduced output current. the csl5 input also serves as the ic? bootstrap sup- ply input. whenever v csl5 > 4.5v, an internal switch connects csl5 to vl. oscillator frequency and synchronization (sync) the sync input controls the oscillator frequency. low selects 200khz; high selects 300khz. sync can also be used to synchronize with an external 5v cmos or ttl clock generator. sync has a guaranteed 240khz to 350khz capture range. a high-to-low transition on sync initiates a new cycle. 300khz operation optimizes the application circuit for component size and cost. 200khz operation provides increased efficiency, lower dropout, and improved load-transient response at low input-output voltage dif- ferences (see the low-voltage operation section).
max1630a?ax1635a multi-output, low-noise power-supply controllers for notebook computers ______________________________________________________________________________________ 15 table 4. operating modes seq run/on3 description x low x all circuit blocks turned off. supply current = 4a. shdn time/on5 x mode shutdown low standby low high ref both smpss off. supply current = 30?. low run high high run low high ref 5v smps enabled/3.3v off. high ref 3.3v smps enabled/5v off. high run high timing capacitor standby low high gnd both smpss off. supply current = 30?. timing capacitor run high timing capacitor standby low high vl both smpss off. supply current = 30?. high high ref both smpss enabled. gnd both smpss enabled. 5v enabled before 3.3v. timing capacitor run high high vl both smpss enabled. 3.3v enabled before 5v. x = don? care. shutdown mode holding shdn low puts the ic into its 4? shutdown mode. shdn is logic input with a threshold of about 1v (the v th of an internal n-channel mosfet). for auto- matic startup, bypass shdn to gnd with a 0.01? capacitor and connect it to v+ through a 220k resistor. power-up sequencing and on/ off controls startup is controlled by run/on3 and time/on5 in conjunction with seq. with seq tied to ref, the two control inputs act as separate on/ off controls for each supply. with seq tied to vl or gnd, run/on3 becomes the master on/ off control input and time/on5 becomes a timing pin, with the delay between the two supplies determined by an external capacitor. the delay is approximately 800?/nf. the +3.3v supply powers up first if seq is tied to vl, and the +5v supply is first if seq is tied to gnd. when driv- ing time/on5 as a control input with external logic, always place a resistor (>1k ) in series with the input. this prevents possible crowbar current due to the inter- nal discharge pulldown transistor, which turns on in standby mode and momentarily at the first power-up or in shutdown mode. reset power-good voltage monitor the power-good monitor generates a system reset sig- nal. at first power-up, reset is held low until both the 3.3v and 5v smps outputs are in regulation. at this point, an internal timer begins counting oscillator pulses, and reset continues to be held low until 32,000 cycles have elapsed. after this timeout period (107ms at 300khz or 160ms at 200khz), reset is actively pulled up to vl. if seq is tied to ref (for separate on3/on5 controls), only the 3.3v smps is monitored?he 5v smps is ignored. output undervoltage shutdown protection (max1630a/max1631a/max1632a) the output undervoltage lockout circuit is similar to foldback current limiting, but employs a timer rather than a variable current limit. each smps has an under- voltage protection circuit that is activated 6144 clock cycles after the smps is enabled. if either smps output is under 70% of the nominal value, both smpss are latched off and their outputs are clamped to ground by the synchronous rectifier mosfets (see the output overvoltage protection section). they do not restart until shdn or run/on3 is toggled, or until v+ power is cycled below 1v. note that undervoltage protection can make prototype troubleshooting difficult, since you have only 20ms or 30ms to figure out what might be wrong with the circuit before both smpss are latched off. in extreme cases, it may be useful to substitute the max1633a/max1634a/max1635a into the prototype breadboard until the prototype is working properly. output overvoltage protection (max1630a/max1631a/max1632a) both smps outputs are monitored for overvoltage. if either output is more than 7% above the nominal regu- lation point, both low-side gate drivers (dl_) are latched high until shdn or run/on3 is toggled, or until v+ power is cycled below 1v. this action turns on the synchronous rectifiers with 100% duty, in turn rapidly discharging the output capacitors and forcing both smps outputs to ground. the dl outputs are also kept high whenever the corresponding smps is disabled, and in shutdown if vl is sustained.
max1630a?ax1635a multi-output, low-noise power-supply controllers for notebook computers 16 ______________________________________________________________________________________ discharging the output capacitor through the main inductor causes the output to momentarily go below gnd. clamp this negative pulse with a back-biased 1a schottky diode across the output capacitor (figure 1). to ensure overvoltage protection on initial power-up, connect signal diodes from both output voltages to vl (cathodes to vl) to eliminate the vl power-up delay. this circuitry protects the load from accidental overvolt- age caused by a short-circuit across the high-side power mosfets. this scheme relies on the presence of a fuse, in series with the battery, which is blown by the resulting crowbar current. note that the overvoltage circuitry will interfere with external keep-alive supplies that hold up the outputs (such as lithium backup or hot- swap power supplies); in such cases, the max1633a, max1634a, or max1635a should be used. low-noise operation (pwm mode) pwm mode ( skip = high) minimizes rf and audio interference in noise-sensitive applications (such as hi- fi multimedia-equipped systems), cellular phones, rf communicating computers, and electromagnetic pen- entry systems. see the summary of operating modes in table 2. skip can be driven from an external logic signal. interference due to switching noise is reduced in pwm mode by ensuring a constant switching frequency, thus concentrating the emissions at a known frequency out- side the system audio or if bands. choose an oscillator frequency for which switching frequency harmonics do not overlap a sensitive frequency band. if necessary, synchronize the oscillator to a tight-tolerance external clock generator. to extend the output-voltage-regula- tion range, constant operating frequency is not main- tained under overload or dropout conditions (see the overload and dropout operation section . ) pwm mode ( skip = high) forces two changes upon the pwm controllers. first, it disables the minimum-current comparator, ensuring fixed-frequency operation. second, it changes the detection threshold for reverse- current limit from 0mv to -100mv, allowing the inductor current to reverse at light loads. this results in fixed- frequency operation and continuous inductor-current flow. this eliminates discontinuous-mode inductor ring- ing and improves cross regulation of transformer- coupled multiple-output supplies, particularly in circuits that do not use additional secondary regulation through secfb or v dd . in most applications, tie skip to gnd to minimize qui- escent supply current. vl supply current with skip high is typically 20ma, depending on external mosfet gate capacitance and switching losses. internal digital soft-start circuit soft-start allows a gradual increase of the internal cur- rent-limit level at startup to reduce input surge currents. both smpss contain internal digital soft-start circuits, each controlled by a counter, a digital-to-analog con- verter (dac), and a current-limit comparator. in shut- down or standby mode, the soft-start counter is reset to zero. when an smps is enabled, its counter starts counting oscillator pulses, and the dac begins incre- menting the comparison voltage applied to the current- limit comparator. the dac output increases from 0mv to 100mv in five equal steps as the count increases to 512 clocks. as a result, the main output capacitor charges up relatively slowly. the exact time of the output rise depends on output capacitance and load current, and is typically 1ms with a 300khz oscillator. dropout operation dropout (low input-output differential operation) is enhanced by stretching the clock pulse width to increase the maximum duty factor. the algorithm fol- lows: if the output voltage (v out ) drops out of regula- tion without the current limit having been reached, the smps skips an off-time period (extending the on-time). at the end of the cycle, if the output is still out of regula- tion, the smps skips another off-time period. this action can continue until three off-time periods are skipped, effectively dividing the clock frequency by as much as four. the typical pwm minimum off-time is 300ns, regardless of the operating frequency. lowering the operating fre- quency raises the maximum duty factor above 98%. adjustable-output feedback (dual mode fb) fixed, preset output voltages are selected when fb_ is connected to ground. adjusting the main output volt- age with external resistors is simple for any of the max1630a family ics, through resistor-dividers con- nected to fb3 and fb5 (figure 2). calculate the output voltage with the following formula: v out = v ref (1 + r1 / r2) where v ref = 2.5v nominal. the nominal output should be set approximately 1% or 2% high to make up for the max1630a? -2% typical load-regulation error. for example, if designing for a 3.0v output, use a resistor ratio that results in a nominal output voltage of 3.05v. this slight offsetting gives the best possible accuracy. recommended normal values for r2 range from 5k to 100k . to achieve a 2.5v nominal output, connect fb_ directly to csl_.
max1630a?ax1635a multi-output, low-noise power-supply controllers for notebook computers ______________________________________________________________________________________ 17 remote output-voltage sensing, while not possible in fixed-output mode due to the combined nature of the voltage-sense and current-sense inputs (csl3 and csl5), is easy to do in adjustable mode by using the top of the external resistor-divider as the remote sense point. when using adjustable mode, it is a good idea to always set the ?.3v output?to a lower voltage than the ?v output.?the 3.3v output must always be less than vl, so that the voltage on csh3 and csl3 is within the common-mode range of the current-sense inputs. while vl is nominally 5v, it can be as low as 4.7v when lin- early regulating, and as low as 4.2v when automatically bootstrapped to csh5. secondary feedback regulation loop (secfb or v dd ) a flyback-winding control loop regulates a secondary winding output, improving cross-regulation when the primary output is lightly loaded or when there is a low input-output differential voltage. if v dd or secfb falls below its regulation threshold, the low-side switch is turned on for an extra 1s. this reverses the inductor (primary) current, pulling current from the output filter capacitor and causing the flyback transformer to oper- ate in forward mode. the low impedance presented by the transformer secondary in forward mode dumps cur- rent into the secondary output, charging up the sec- ondary capacitor and bringing v dd or secfb back into regulation. the secondary feedback loop does not improve secondary output accuracy in normal flyback mode, where the main (primary) output is heavily loaded. in this condition, secondary output accuracy is determined by the secondary rectifier drop, transformer turns ratio, and accuracy of the main output voltage. a linear postregulator may still be needed to meet strict output-accuracy specifications. devices with a 12out linear regulator have a v dd pin that regulates at a fixed 13.5v, set by an internal resistor-divider. the max1631a/max1634a have an adjustable secondary output voltage set by an external- resistor-divider on secfb (figure 5). ordinarily, the secondary regulation point is set 5% to 10% below the voltage normally produced by the flyback effect. for example, if the output voltage as determined by turns ratio is 15v, set the feedback resistor ratio to produce 13.5v. otherwise, the secfb one-shot might be trig- gered unintentionally, unnecessarily increasing supply current and output noise. 12v linear regulator output (max1630a/max1632a/ max1633a/max1635a) the max1630a/max1632a/max1633a/max1635a include a 12v linear regulator output capable of deliver- ing 120ma of output current. typically, greater current is available at the expense of output accuracy. if an accu- max1631a max1634a positive secondary output main output dh_ v+ secfb 2.5v ref r2 r1 1-shot trig dl_ where v ref (nominal) = 2.5v +v trip = v ref ( 1 + ) r1 r2 figure 5. adjusting the secondary output voltage with secfb max1630a max1632a max1633a max1635a v dd output +12v output 200ma main output 2n3906 0.1 f 0.1 f 0.1 f 2.2 f 10 f 10 v+ v dd 12out dh_ dl_ figure 6. increased 12v linear regulator output current
max1630a?ax1635a multi-output, low-noise power-supply controllers for notebook computers 18 ______________________________________________________________________________________ kool-m is a registered trademark of magnetics div., spang & co. rate output of more than 120ma is needed, an external pass transistor can be added. figure 6? circuit delivers more than 200ma. total output current is constrained by the v+ input voltage and the transformer primary load (see maximum 15v v dd output current vs. supply voltage graphs in the typical operating characteristics ). __________________design procedure the three predesigned 3v/5v standard application cir- cuits (figure 1 and table 1) contain ready-to-use solu- tions for common application needs. also, two standard flyback transformer circuits support the 12out linear regulator in the applications information section. use the following design procedure to optimize these basic schematics for different voltage or current require- ments. before beginning a design, firmly establish the following: maximum input (battery) voltage, v in(max) . this value should include the worst-case conditions, such as no-load operation when a battery charger or ac adapter is connected but no battery is installed. v in(max) must not exceed 30v. minimum input (battery) voltage, v in(min) . this should be taken at full load under the lowest battery conditions. if v in(min) is less than 4.2v, use an external circuit to externally hold vl above the vl undervoltage lockout threshold. if the minimum input-output difference is less than 1.5v, the filter capacitance required to maintain good ac load regulation increases (see low-voltage operation section). inductor value the exact inductor value is not critical and can be freely adjusted to make trade-offs between size, cost, and efficiency. lower inductor values minimize size and cost, but reduce efficiency due to higher peak-cur- rent levels. the smallest inductor is achieved by lower- ing the inductance until the circuit operates at the border between continuous and discontinuous mode. further reducing the inductor value below this crossover point results in discontinuous-conduction operation even at full load. this helps lower output filter capacitance requirements, but efficiency suffers due to high i 2 r losses. on the other hand, higher inductor val- ues mean greater efficiency, but resistive losses due to extra wire turns will eventually exceed the benefit gained from lower peak-current levels. also, high inductor values can affect load-transient response (see the v sag equation in the low-voltage operation sec- tion). the equations that follow are for continuous-con- duction operation, since the max1630a family is intended mainly for high-efficiency, battery-powered applications. refer to appendix a in maxim? battery management and dc-dc converter circuit collection for crossover-point and discontinuous-mode equations. discontinuous conduction doesn? affect normal idle mode operation. three key inductor parameters must be specified: inductance value (l), peak current (i peak ), and dc resistance (r dc ). the following equation includes a constant, lir, which is the ratio of inductor peak-to- peak ac current to dc load current. a higher lir value allows smaller inductance, but results in higher losses and higher ripple. a good compromise between size and losses is found at a 30% ripple-current to load- current ratio (lir = 0.3), which corresponds to a peak inductor current 1.15 times higher than the dc load current: where: f = switching frequency, normally 200khz or 300khz i out = maximum dc load current lir = ratio of ac to dc inductor current, typi- cally 0.3; should be selected for >0.15 the nominal peak inductor current at full load is 1.15 x i out if the above equation is used; otherwise, the peak current can be calculated by: the inductor? dc resistance should be low enough that r dc x i peak < 100mv, as it is a key parameter for effi- ciency performance. if a standard off-the-shelf inductor is not available, choose a core with an li 2 rating greater than l x i peak 2 and wind it with the largest diameter wire that fits the winding area. for 300khz applications, ferrite core material is strongly preferred; for 200khz applications, kool-m (aluminum alloy) or even pow- dered iron is acceptable. if light-load efficiency is unim- portant (in desktop pc applications, for example), then low-permeability iron-powder cores, such as the micrometals type found in pulse engineering? 2.1? pe-53680, may be acceptable even at 300khz. for high-current applications, shielded-core geometries, such as toroidal or pot core, help keep noise, emi, and switching-waveform jitter low. i= i+ v (v -v 2 x f x l x v peak load out in(max) out in(max) ) l = vv - v v x f x i x lir out in(max) out in(max) out ()
max1630a?ax1635a multi-output, low-noise power-supply controllers for notebook computers ______________________________________________________________________________________ 19 current-sense resistor value the current-sense resistor value is calculated according to the worst-case-low current-limit threshold voltage (from the electrical characteristics table) and the peak inductor current: use i peak from the second equation in the inductor value section use the calculated value of r sense to size the mosfet switches and specify inductor saturation-current ratings according to the worst-case high-current-limit threshold voltage: low-inductance resistors, such as surface-mount metal-film, are recommended. input capacitor value connect low-esr bulk capacitors and small ceramic capacitors (0.1?) directly to the drains on the high-side mosfets. the bulk input filter capacitor is usually selected according to input ripple current requirements and voltage rating, rather than capacitor value. electrolytic capacitors with low enough effective series resistance (esr) to meet the ripple current requirement invariably have sufficient capacitance values. aluminum electrolytic capacitors, such as sanyo os-con or nichicon pl, are superior to tantalum types, which carry the risk of power-up surge-current failure, especially when connecting to robust ac adapters or low-impedance batteries. rms input ripple current (i rms ) is determined by the input voltage and load cur- rent, with the worst case occurring at v in = 2 x v out : bypassing v+ bypass the v+ input with a 4.7? tantalum capacitor paralleled with a 0.1? ceramic capacitor, close to the ic. a 10 series resistor to v in is also recommended. bypassing vl bypass the vl output with a 4.7? tantalum capacitor paralleled with a 0.1? ceramic capacitor, close to the device. output filter capacitor value the output filter capacitor values are generally deter- mined by the esr and voltage rating requirements, rather than actual capacitance requirements for loop stability. in other words, the low-esr electrolytic capacitor that meets the esr requirement usually has more output capaci- tance than is required for ac stability. use only special- ized low-esr capacitors intended for switching-regulator applications, such as avx tps, sprague 595d, sanyo os-con, or nichicon pl series. to ensure stability, the capacitor must meet both minimum capacitance and maximum esr values as given in the following equations: (can be multiplied by 1.5; see text below) these equations are worst case, with 45 degrees of phase margin to ensure jitter-free, fixed-frequency operation and provide a nicely damped output response for zero to full-load step changes. some cost- conscious designers may wish to bend these rules with less-expensive capacitors, particularly if the load lacks large step changes. this practice is tolerable if some bench testing over temperature is done to verify acceptable noise and transient response. no well-defined boundary exists between stable and unstable operation. as phase margin is reduced, the first symptom is a bit of timing jitter, which shows up as blurred edges in the switching waveforms where the scope does not quite sync up. technically speaking, this jitter (usually harmless) is unstable operation, since the duty factor varies slightly. as capacitors with higher esrs are used, the jitter becomes more pronounced, and the load-transient output voltage waveform starts looking ragged at the edges. eventually, the load-tran- sient waveform has enough ringing on it that the peak noise levels exceed the allowable output voltage toler- ance. note that even with zero phase margin and gross instability present, the output voltage noise never gets much worse than i peak x r esr (under constant loads). designers of rf communicators or other noise-sensi- tive analog equipment should be conservative and stay within the guidelines. designers of notebook computers and similar commercial-temperature-range digital systems can multiply the r esr value by a factor of 1.5 without hurting stability or transient response. the output voltage ripple is usually dominated by the filter capacitor? esr, and can be approximated as i ripple x r esr . there is also a capacitive term, so the c> v (1 + v / v ) v x r x f < out ref out in(min) out sense r rxv v esr sense out ref i = i x v(v-v) v i i 2 rms load out in out in rms load therefore when v is x v in out ,: 2 = i = 120mv r peak(max) sense r = 80mv i sense peak
max1630a?ax1635a multi-output, low-noise power-supply controllers for notebook computers 20 ______________________________________________________________________________________ full equation for ripple in continuous-conduction mode is v noise (p-p) = i ripple x [r esr + 1/(2 x x f x c out )]. in idle mode, the inductor current becomes discontinuous, with high peaks and widely spaced pulses, so the noise can actually be higher at light load (compared to full load). in idle mode, calculate the out- put ripple as follows: transformer design (for auxiliary outputs only) buck-plus-flyback applications, sometimes called ?ou- pled-inductor?topologies, need a transformer to gener- ate multiple output voltages. performing the basic electrical design is a simple task of calculating turns ratios and adding the power delivered to the secondary to calculate the current-sense resistor and primary inductance. however, extremes of low input-output dif- ferentials, widely different output loading levels, and high turns ratios can complicate the design due to par- asitic transformer parameters such as interwinding capacitance, secondary resistance, and leakage inductance. for examples of what is possible with real- world transformers, see the maximum secondary current vs. input voltage graph in the typical operating characteristics section. power from the main and secondary outputs is combined to get an equivalent current referred to the main output voltage (see the inductor value section for parameter def- initions). set the current-sense resistor resistor value at 80mv / i total . p total = the sum of the output power from all outputs i total = p total / v out = the equivalent output cur- rent referred to v out : where: v sec = the minimum required rectified secondary out- put voltage v fwd = the forward drop across the secondary rectifier vout(min) = the minimum value of the main output voltage (from the electrical characteristics) v rect = the on-state voltage drop across the synchro- nous rectifier mosfet v sense = the voltage drop across the sense resistor in positive-output applications, the transformer sec- ondary return is often referred to the main output volt- age, rather than to ground, to reduce the needed turns ratio. in this case, the main output voltage must first be subtracted from the secondary voltage to obtain v sec . selecting other components mosfet switches the high-current n-channel mosfets must be logic-level types with guaranteed on-resistance specifications at v gs = 4.5v. lower gate threshold specifications are bet- ter (i.e., 2v max rather than 3v max). drain-source break- down voltage ratings must at least equal the maximum input voltage, preferably with a 20% derating factor. the best mosfets have the lowest on-resistance per nanocoulomb of gate charge. multiplying r ds(on) x q g provides a good figure for comparing various mosfets. newer mosfet process technologies with dense cell structures generally perform best. the internal gate dri- vers tolerate >100nc total gate charge, but 70nc is a more practical upper limit to maintain best switching times. in high-current applications, mosfet package power dissipation often becomes a dominant design factor. i 2 r power losses are the greatest heat contributor for both high-side and low-side mosfets. i 2 r losses are distrib- uted between q1 and q2 according to duty factor (see the following equations). generally, switching losses affect only the upper mosfet, since the schottky rectifier clamps the switching node in most cases before the syn- chronous rectifier turns on. gate-charge losses are dissi- pated by the driver and do not heat the mosfet. calculate the temperature rise according to package thermal-resistance specifications to ensure that both mosfets are within their maximum junction temperature at high ambient temperature. the worst-case dissipation for the high-side mosfet occurs at both extremes of input voltage, and the worst-case dissipation for the low- side mosfet occurs at maximum input voltage: pd(upper fet) = (i ) x r x duty + v x i x f x v x c i 20ns pd(lower fet) = (i ) x r x (1 - duty) duty = (v + v ) / (v - v ) load 2 ds(on) in load in rss gate load 2 ds(on) out q2 in q1 + ? ? ? ? ? ? l(primary) = v(v -v) v x f x i x lir turns ratio n = v + v v+v+v out in(max) out in(max) total sec fwd out(min) rect sense v = 0.02 x r r 0.0003 x lx 1 / v 1 / (v - v ) (r ) x c noise(p-p) esr sense out in out sense 2 out + + []
max1630a?ax1635a multi-output, low-noise power-supply controllers for notebook computers ______________________________________________________________________________________ 21 where: on-state voltage drop v q_ = i load x r ds(on) c rss = mosfet reverse transfer capacitance i gate =dh driver peak output current capability (1a typical) 20ns = dh driver inherent rise/fall time under output short circuit, the max1633a/max1634a/ max1635as?synchronous rectifier mosfet suffers extra stress because its duty factor can increase to greater than 0.9. it may need to be oversized to tolerate a continuous dc short circuit. during short circuit, the max1630a/max1631a/max1632as?output undervolt- age shutdown protects the synchronous rectifier under output short-circuit conditions. to reduce emi, add a 0.1? ceramic capacitor from the high-side switch drain to the low-side switch source. rectifier clamp diode the rectifier is a clamp across the low-side mosfet that catches the negative inductor swing during the 60ns dead time between turning one mosfet off and each low-side mosfet on. the latest generations of mosfets incorporate a high-speed silicon body diode, which serves as an adequate clamp diode if efficiency is not of primary importance. a schottky diode can be placed in parallel with the body diode to reduce the for- ward voltage drop, typically improving efficiency 1% to 2%. use a diode with a dc current rating equal to one- third of the load current; for example, use an mbr0530 (500ma-rated) type for loads up to 1.5a, a 1n5819 type for loads up to 3a, or a 1n5822 type for loads up to 10a. the rectifier? rated reverse breakdown voltage must be at least equal to the maximum input voltage, preferably with a 20% derating factor. boost-supply diode d2 a signal diode such as a 1n4148 works well in most applications. if the input voltage can go below +6v, use a small (20ma) schottky diode for slightly improved efficiency and dropout characteristics. do not use large power diodes, such as 1n5817 or 1n4001, since high junction capacitance can pump up vl to excessive voltages. rectifier diode d3 (transformer secondary diode) the secondary diode in coupled-inductor applications must withstand flyback voltages greater than 60v, which usually rules out most schottky rectifiers. common silicon rectifiers, such as the 1n4001, are also prohibited because they are too slow. this often makes fast silicon rectifiers such as the murs120 the only choice. the flyback voltage across the rectifier is relat- ed to the v in - v out difference, according to the trans- former turns ratio: where: n = the transformer turns ratio sec/pri v sec = the maximum secondary dc output voltage v out = the primary (main) output voltage subtract the main output voltage (v out ) from v flyback in this equation if the secondary winding is returned to v out and not to ground. the diode reverse breakdown rating must also accommodate any ringing due to leak- age inductance. d3? current rating should be at least twice the dc load current on the secondary output. low-voltage operation low input voltages and low input-output differential voltages each require extra care in their design. low absolute input voltages can cause the vl linear regula- tor to enter dropout and eventually shut itself off. low input voltages relative to the output (low v in -v out dif- ferential) can cause bad load regulation in multi-output flyback applications (see the design equations in the transformer design section). also, low v in -v out differ- entials can also cause the output voltage to sag when the load current changes abruptly. the amplitude of the sag is a function of inductor value and maximum duty factor (an electrical characteristics parameter, 98% guaranteed over temperature at f = 200khz), as follows: the cure for low-voltage sag is to increase the output capacitor? value. for example, at v in = +5.5v, v out = +5v, l = 10?, f = 200khz, i step = 3a, a total capaci- tance of 660? keeps the sag less than 200mv. note that only the capacitance requirement increases, and the esr requirements do not change. therefore, the added capacitance can be supplied by a low-cost bulk capacitor in parallel with the normal low-esr capacitor. v= (i ) x l 2 x c x (v x d - v ) sag step 2 out in(max) max out v = v + (v - v ) x n flyback sec in out
max1630a?ax1635a multi-output, low-noise power-supply controllers for notebook computers 22 ______________________________________________________________________________________ table 5. low-voltage troubleshooting chart ________________ applications information heavy-load efficiency considerations the major efficiency-loss mechanisms under loads are, in the usual order of importance: ? p(i 2 r) = i 2 r losses ? p(tran) = transition losses ? p(gate) = gate-charge losses ? p(diode) = diode-conduction losses ? p(cap) = capacitor esr losses ? p(ic) = losses due to the ic? operating supply current inductor core losses are fairly low at heavy loads because the inductor? ac current component is small. therefore, they are not accounted for in this analysis. ferrite cores are preferred, especially at 300khz, but powdered cores, such as kool-mu, can work well: where r dc is the dc resistance of the coil, r ds(on) is the mosfet on-resistance, and r sense is the current- sense resistor value. the r ds(on) term assumes identi- cal mosfets for the high-side and low-side switches, because they time-share the inductor current. if the mosfets are not identical, their losses can be estimat- ed by averaging the losses according to duty factor: where c rss is the reverse transfer capacitance of the high-side mosfet (a data-sheet parameter), i gate is the dh gate-driver peak output current (1.5a typ), and 20ns is the rise/fall time of the dh driver (20ns typ): p(gate) = qg x f x vl where vl is the internal-logic-supply voltage (+5v), and qg is the sum of the gate-charge values for low-side and high- side switches. for matched mosfets, qg is twice the data-sheet value of an individual mosfet. if v out is set to less than 4.5v, replace vl in this equation with v batt . in this case, efficiency can be improved by connecting vl to an efficient 5v source, such as the system +5v supply: p(diode) = diode - conduction losses = i x v x t x f load fwd d pd(tran) = transition loss = v x i x f x 3 2 x (v x c / i ) + 20ns in load in rss gate [] efficiency = p / p x 100% = p / (p + p ) x 100% p = p(i r) + p(tran) + p(gate) + p(diode) + p(cap) + p(ic) p = (i r) = (i ) x (r + r + r ) out in out out total total 2 2 load 2 dc ds(on) sense use a small 20ma schottky diode for boost diode d2. supply vl from an external source. poor efficiency vl linear regulator is going into dropout and is not pro- viding good gate-drive lev els. supply vl from an external source other than v in , such as the system +5v supply. does not start under load or quits before battery is completely dead low input voltage, <5v vl output is so low that it hits the vl uvlo threshold. low input voltage, <4.5v increase the minimum input voltage or ignore. unstable?itters between different duty factors and frequencies normal function of internal low-dropout circuitry. reduce operation to 200khz. reduce secondary impedances; use a schottky diode, if possible. stack secondary winding on the main output. secondary output won? support a load low v in -v out differential, <0.5v not enough duty cycle left to initiate forward-mode opera- tion. small ac current in primary cannot store energy for flyback opera tion. low v in -v out differential, v in < 1.3 x v out (main) reduce operation to 200khz. reduce mosfet on-resistance and coil dcr. dropout voltage is too high (v out follows v in as v in decreases) maximum duty-cycle limits exceeded. low v in -v out differential, <1v increase bulk output capacitance per formula (see the low-voltage operation section). reduce inductor value. solution limited inductor-current slew rate per cycle. root cause low v in -v out differential, <1.5v condition sag or droop in v out under step-load change symptom
max1630a?ax1635a multi-output, low-noise power-supply controllers for notebook computers ______________________________________________________________________________________ 23 where t d is the diode-conduction time (120ns typ) and v fwd is the forward voltage of the diode. this power is dissipated in the mosfet body diode if no external schottky diode is used: where i rms is the input ripple current as calculated in the design procedure and input capacitor value sections. light-load efficiency considerations under light loads, the pwm operates in discontinuous mode, where the inductor current discharges to zero at some point during the switching cycle. this makes the inductor current? ac component high compared to the load current, which increases core losses and i 2 r loss- es in the output filter capacitors. for best light-load effi- ciency, use mosfets with moderate gate-charge levels, and use ferrite, mpp, or other low-loss core material. avoid powdered-iron cores; even kool-mu (aluminum alloy) is not as good as ferrite. pc board layout considerations good pc board layout is required in order to achieve specified noise, efficiency, and stability performance. the pc board layout artist must be given explicit instructions, preferably a pencil sketch showing the placement of power-switching components and high- current routing. refer to the pc board layout in the max1630a evaluation kit manual for examples. a ground plane is essential for optimum performance. in most applications, the circuit will be located on a multilayer board, and full use of the four or more cop- per layers is recommended. use the top layer for high- current connections, the bottom layer for quiet connections (ref, ss, gnd), and the inner layers for an uninterrupted ground plane. use the following step- by-step guide: 1) place the high-power components (figure 1, c1, c3, q1, q2, d1, l1, and r1) first, with any grounded connections adjacent: priority 1: minimize current-sense resistor trace lengths and ensure accurate current sensing with kelvin connections (figure 7). priority 2: minimize ground trace lengths in the high-current paths (discussed below). priority 3: minimize other trace lengths in the high- current paths. use > 5mm-wide traces. c in to high-side mosfet drain: 10mm max length. rectifier diode cathode to low-side mosfet: 5mm max length. lx node (mosfets, rectifier cathode, inductor): 15mm max length. ideally, surface-mount power components are butted up to one another with their ground terminals almost touching. these high-current grounds are then con- nected to each other with a wide filled zone of top-layer copper so they do not go through vias. the resulting top-layer ?ubground-plane?is connected to the normal inner-layer ground plane at the output ground termi- nals, which ensures that the ic? analog ground is sensing at the supply? output terminals without interfer- ence from ir drops and ground noise. other high- current paths should also be minimized, but focusing primarily on short ground and current-sense con- nections eliminates about 90% of all pc board lay- out problems (refer to the pc board layouts in the max1630a evaluation kit manual for examples). 2) place the ic and signal components. keep the main switching nodes (lx nodes) away from sensitive analog components (current-sense traces and ref capacitor). place the ic and analog components on the opposite side of the board from the power- switching node. important: the ic must be no far- ther than 10mm from the current-sense resistors. keep the gate-drive traces (dh_, dl_, and bst_) shorter than 20mm and route them away from csh_, csl_, and ref. 3) use a single-point star ground where the input ground trace, power ground (subground-plane), and normal ground plane meet at the supply? out- put ground terminal. connect both ic ground pins and all ic bypass capacitors to the normal ground plane. p(cap) = input capacitor esr loss = (i ) x r rms 2 esr max1630a sense resistor high-current path figure 7. kelvin connections for the current-sense resistors
max1630a?ax1635a multi-output, low-noise power-supply controllers for notebook computers 24 ______________________________________________________________________________________ _______________________________________________________________________________ application circuits reset fb5 max1630a max1633a shdn sync input +5.2v to +24v pgnd seq ref 11 9 15 12 13 14 20 19 17 16 q3 q4 l2 r2 c2 18 4 23 22 10 621 power-good 7 10 8 5v on/off skip v+ vl dl5 lx5 dh5 bst5 2.2 f 0.1 f 0.1 f 0.1 f 1 f 0.1 f 4.7 f 2.7 f 1n5819 4.7 f 12out c3 c4 +12v at 120ma +5v output (3a) +5v always on gnd +2.5v ref 3 * 2 1 24 q1 q2 t1 1:4 c1 r1 5 0.1 f 0.1 f 1n5819 +3.3v output (3a) * time/on5 run/on3 fb3 28 3v on/off 26 25 27 csl5 csh5 csl3 csh3 dl3 lx3 dh3 bst3 v dd on/off to +3.3v output to +5v output r1 = r2 = 20m l2 = 10 h sumida cdrh125-100 t1 = 10 h 1:4 transformer transpower technologies tti-5902 q1?4 = si4410dy or irf7413 c1 = 3 x 220 f 10v sprague 594d227x0010d2t c2 = 2 x 220 f 10v sprague 594d227x0010d2t c3 = c4 = 2 x 10 f 30v sanyo os-con 30sc10m *vl diodes and output schottky diodes required for the max1630a only (see output overvoltage protection and output undervoltage shutdown protection sections). * * figure 8. triple-output application for low-voltage batteries (max1630a/max1633a)
max1630a?ax1635a multi-output, low-noise power-supply controllers for notebook computers ______________________________________________________________________________________ 25 _____________________________________________________________ application circuits (continued) 2.2 f 5 reset fb5 max1632a max1635a pgnd seq ref 11 9 15 12 13 14 20 19 17 16 q3 q4 t2 1:2.2 r2 d5 d2 18 power-good 7 10 8 5v on/off skip dl5 lx5 dh5 bst5 v dd 2.2 f 0.1 f c2 0.1 f 1 f 1n5819 +5v output (3a) gnd +2.5v ref 3 * 2 1 24 q1 d1 q2 l1 r1 0.1 f 0.1 f 1n5819 +3.3v output (3a) on/off * time/on5 run/on3 fb3 28 3v on/off 26 25 27 csl5 csh5 csl3 csh3 dl3 lx3 dh3 bst3 shdn sync input +6.5v to +28v 4 23 22 10 621 v+ vl 0.1 f 0.1 f 4.7 f 4.7 f 12out c3 c1 c4 to +3.3v output to +5v output +12v at 120ma +5v always on r1 = r2 = 20m l1 = 10 h sumida cdrh125-100 t2 = 10 h 1:2.2 transformer transpower technologies tti-5870 q1?4 = si4410dy or irf7413 c1 = 3 x 220 f 10v sprague 594d227x0010d2t c2 = 2 x 220 f 10v sprague 594d227x0010d2t c3 = c4 = 2 x 10 f 30v sanyo os-con 30sc10m *vl diodes and output schottky diodes required for the max1632a only (see output overvoltage protection and output undervoltage shutdown protection sections). * * figure 9. triple-output application for high-voltage batteries (max1632a/max1635a)
max1630a?ax1635a multi-output, low-noise power-supply controllers for notebook computers 26 ______________________________________________________________________________________ open max1631a max1634a v+ shdn vl secfb input +6v to +24v c3 10 on/off gnd ref seq sync 1 f 5v always on q1 on/off on/off 0.1 f 0.1 f 4.7 f 4.7 f 0.1 f q3 dl3 csh3 csl3 fb3 reset reset output skip steer l1 r1 2.5v output c1 dl5 lx5 dh5 bst5 25 27 26 24 1 2 3 11 10 4 8 28 7 12 13 14 20 19 17 16 18 22 23 5 21 15 6 9 bst3 dh3 lx3 pgnd csl5 csh5 run/on3 time/on5 0 fb5 0.1 f 0.1 f l2 r2 +3.3v output r1 = r2 = 15m l1 = l2 = 6.8 h sumida cdrh 127-6r8mc q1 = q4 = si4410dy or 1rf7413 c1 = c2 = 2x sanyo os-con 10 sa220m c3 = 4x sanyo os-con 30sc10m *vl diodes and output schottky diodes required for the max1631a only (see output overvoltage protection and output undervoltage shutdown protection sections). * * * open 0 * q4 1n5819 q2 1n5819 c2 figure 10. dual, 4a, notebook computer power supply _____________________________________________________________ application circuits (continued)
max1630a?ax1635a multi-output, low-noise power-supply controllers for notebook computers ______________________________________________________________________________________ 27 ________________________________________________________________________________ pin configurations 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 run/on3 dh3 lx3 bst3 dl3 shdn seq v+ vl pgnd dl5 bst5 lx5 dh5 csh5 csl5 fb5 reset skip ref gnd time/on5 sync v dd 12out fb3 csl3 csh3 ssop ssop max1630a max1632a max1633a max1635a 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 run/on3 dh3 lx3 bst3 dl3 shdn seq v+ vl pgnd dl5 bst5 lx5 dh5 csh5 csl5 fb5 reset skip ref gnd time/on5 sync secfb steer fb3 csl3 csh3 top view max1631a max1634a _______________________________________________________________selector guide max1631a max1633a max1632a max1634a max1635a device none (secfb input) 12v linear regulator 12v linear regulator none (secfb input) 12v linear regulator auxiliary output 12v linear regulator selectable (steer pin) feeds into the 3.3v smps feeds into the 5v smps selectable (steer pin) feeds into the 5v smps secondary feedback yes no yes no max1630a no over/undervoltage protection yes feeds into the 3.3v smps
max1630a?ax1635a multi-output, low-noise power-supply controllers for notebook computers 28 ______________________________________________________________________________________ __ordering information (continued) + denotes lead-free package. 28 ssop -40? to +85? max1635a eai 28 ssop -40? to +85? 28 ssop -40? to +85? max1634a eai max1633a eai 28 ssop -40? to +85? max1632a eai 28 ssop pin-package temp range -40? to +85? max1630aeai+ part 28 ssop -40? to +85? max1631a eai 28 ssop -40? to +85? MAX1631AEAI+ 28 ssop -40? to +85? max1632aeai+ 28 ssop -40? to +85? max1633aeai+ 28 ssop -40? to +85? max1634aeai+ 28 ssop -40? to +85? max1635aeai+
max1630a?ax1635a multi-output, low-noise power-supply controllers for notebook computers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 29 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. ssop.eps package outline, ssop, 5.3 mm 1 1 21-0056 c rev. document control no. approval proprietary information title: notes: 1. d&e do not include mold flash. 2. mold flash or protrusions not to exceed .15 mm (.006"). 3. controlling dimension: millimeters. 4. meets jedec mo150. 5. leads to be coplanar within 0.10 mm. 7.90 h l 0 0.301 0.025 8 0.311 0.037 0 7.65 0.63 8 0.95 max 5.38 millimeters b c d e e a1 dim a see variations 0.0256 bsc 0.010 0.004 0.205 0.002 0.015 0.008 0.212 0.008 inches min max 0.078 0.65 bsc 0.25 0.09 5.20 0.05 0.38 0.20 0.21 min 1.73 1.99 millimeters 6.07 6.07 10.07 8.07 7.07 inches d d d d d 0.239 0.239 0.397 0.317 0.278 min 0.249 0.249 0.407 0.328 0.289 max min 6.33 6.33 10.33 8.33 7.33 14l 16l 28l 24l 20l max n a d e a1 l c h e n 1 2 b 0.068 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)

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